The present invention relates to a memory device and, more particularly, to a read only memory (hereinafter referred to as "ROM") which is incorporated in such an information processor as a microcomputer and comprising complementary type metal oxide film semiconductors.
When it is necessary to read out data stored in a memory device at a high speed, for instance, when a high speed operation is required in a device such as a microcomputer incorporating a ROM in which a program to be executed is stored and also it is necessary to read out stored data at a high speed, generally a current sense amplifier is adopted as a circuit which detects and outputs the data stored in a memory cell.
FIG. 5 is a circuit diagram showing a portion of a memory cell and an example of a conventional current sense amplifier. In this diagram, A1 and A2 are address lines; D1 is a data line; Q101 and Q102 are memory cells consisting of n-channel MOS transistors (hereinafter referred to as "nMOS"); 1a is a current sense amplifier consisting of nMOSs Q1, Q2, p-channel MOS transistors (hereinafter referred to as "pMOS") Q11, Q12, and inverters I1, I7; and 2a is a reference voltage generating circuit consisting of nMOSs Q3 to Q5, nMOSs Q13, Q14; and an inverter I8, which supplies a reference voltage to the current sense amplifier 1a.
Explanation is hereunder made for actual operations of the conventional circuit shown in FIG. 5. If it is assumed that the address line A1 is set to a high level (power supply voltage V.sub.DD level) and the address line A2 to a low level (GND level), then the memory cell Q101 with the address line A1 as a gate input turns ON, while the memory cell 102 with the address line A2 as a gate input turns OFF. As the memory cell Q101 is not connected to the data line D1. However, an impedance viewed from a node N1 to the direction of the data line D1 is infinite. Under this state, the pMOS Q11 turns ON, but a current path for this transistor is not established, so that a voltage at the node N1 is V.sub.DD -V.sub.TP (V.sub.TP being a threshold voltage for the pMOS (Q11) and being approximately 0.8 V). As the node N1 is connected to a gate of the pMOS Q12, the pMOS Q12 is kept substantially OFF, and as a voltage enough for this nMOS Q2 to turn ON as described later is supplied to a gate of the nMOS Q2 from the reference voltage generating circuit 2a under this state, the node N2 goes down to the low level. Thus, the high level output is obtained as stored data from an output terminal of the inverter circuit I1.
To the contrary, if the address line A2 is at the high level and the address line A1 at the low level, the memory cell Q102 turns ON, so that a steady-state current flows from the V.sub.DD power source through the pMOS Q11, the nMOS Q1, the data line D1, the memory cell Q102 to the ground. For this reason, a potential at the node N1 becomes closer to the GND potential than to the potential V.sub.DD -V.sub.PT which is determined by a ratio of ON resistance of the memory cell Q102, the nMOS Q1 and the pMOS Q11. This potential is sufficiently large for the pMOS Q12 to turn ON, so that the potential at the node N2 becomes closer to the potential V.sub.DD and the low level output is obtained as stored data from the output terminal of the inverter circuit I1.
From the reference voltage generating circuit 2a, a reference voltage determined according to a ratio of ON resistance of the nMOS Q5 and that of the pMOS Q14 is outputted. Also, a voltage determined by a ratio of ON resistance of the nMOSs Q3 and Q4 as well as the pMOS Q13 is applied to a gate of the pMOS Q14, and the reference voltage is controlled so that the nMOS Q2 turns ON and the low level output or the high level output is outputted at the node N2 according to the voltage appearing at the node N1.
As described above, the current sense amplifier determines whether an nMOS (memory cell) is connected to the data line D1 or not, by detecting whether a current is flowing through the current path or not, and reads out the stored data as a logic value. So it can immediately read out the data stored in the accessed or specified memory cell when any address line is active, thus enabling high speed read-out operation of the data.
In the memory cell device described above, in the reference voltage generating circuit 2a, a steady-state current is flowing through the current path consisting of the nMOSs Q3, Q4 and the pMOS Q13, and also a steady-state current is flowing through the circuit consisting of the nMOS Q5 and the pMOS Q14. Also, in the current sense amplifier 1a, a steady-state current is flowing in the current path consisting of the nMOS Q1 and the pMOS Q11 and in the current path consisting of the nMOS Q2 and the pMOS Q12.
In a microcomputer, data is stored by 8 bits as a unit in a ROM, and read-out is also made by 8 bits as a unit, so that eight (8) current sense amplifiers are required. A steady-state current which flows in one current sense amplifier is approximately 200 .mu.A under the state where the power supply voltage V.sub.DD is 5 V. For this reason, in the entire current sense amplifier circuit per data unit, although it depends on a quantity of the data stored in the memory cell, a current of around 1 mA flows steadily. This current flows steadily irrespective of a processing operation frequency (clock frequency) in the microcomputer so that, in applications where, for instance, a high speed processing operation is not required but the power consumption must be low (e.g., an application where a battery back-up is provided in case of power failure, or an application in which a battery is used as a power source), the power consumption is too high. This means that such a conventional memory device lacks utility for general purpose microcomputers.